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Creators/Authors contains: "Walling, Jeffrey S"

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  1. ; (, Proceedings of the Annual Government Microcircuit Applications & Critical Technology Conference (GOMACTech))
    Digital-to-Analog Converters (DACs) are inseparable fundamental components in radios that act as translator between digital signal processing and all types of transmitters including software-defined radios. Current Steering DACs (CS-DACs) are of interest because of their good linearity and high speed. In this article, a modification to the switching of a segmented CS-DAC is proposed through the use of a sub-DAC. The proposed techniques not only allow for reduced die area but also reduce power consumption while the static nonlinearity can be kept similar to the conventional segmented CS-DACs. The MATLAB model of the proposed DAC is tested for the performance of the 7 bit DAC under ideal and non-ideal cases and implemented in 22nm FDSOI technology with forward body biasing. The total power consumption of the proposed DAC is 2.4mW and it achieved FoM of 433. 
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    Free, publicly-accessible full text available March 19, 2026
  2. ; ; (, IEEE (Proceedings of the 2024 IEEE NEWCAS Conference))
    This paper presents the design and performance evaluation of a class of Phase-Frequency Detectors (PFDs) implemented utilizing only logic gates. It is a suitable candidate for applications like All-Digital Phase-Locked Loops (ADPLLs) and Delay-Locked Loops (DLLs). The proposed design is laid out in 65 nm CMOS and 22 nm FD-SOI technology and it is validated using post-extracted simulations. According to the results the proposed PFD is blind zone free and exhibits a small dead zone of ≈ 7 ps and ≈ 9 ps with a detection range of ±2π at a frequency of 10 GHz and 8 GHz in 22 nm and 65 nm, respectively. The proposed design has jitter ≈ 448 fs in 22 nm and ≈ 1.2 ps in 65 nm. The proposed PFD occupies a layout area of 115.625 μm2 and consumes 7.2 μW in 22nm and the area of the design is 225.7 μm2 and consumes 11.03 μW in 65nm. 
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    Accepted Manuscript Full Text Available
  3. ; ; ; (, IEEE (Proceedings of the 2024 IEEE NEWCAS Conference))
    This paper introduces an automatic amplitude control (AAC) mechanism implemented on a class-C LC-based phase shifter. The AAC technique compensates for the amplitude attenuation of the phase shifter as a function of frequency and provides output swing control that enhances the suitability as a phase shifter in the auxiliary path of a load-modulated balanced power amplifier (LMB-PA). It can be utilized to calibrate and fine-tune the power amplifier (PA) performance after fabrication to achieve optimal performance. The circuit is designed and laid out using 22−nm FD-SOI process technology. To demonstrate the proposed idea, the frequency of operation was chosen as 2.4 GHz. The total power consumption varies between 0.52 − 1 mW due to phase control from 0 − 120◦ with 0.085 dB amplitude error. 
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    Accepted Manuscript Full Text Available
  4. ; ; ; (, NEWCAS)
  5. ; (, 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC))
    This paper presents a multiphase switched-capacitor power amplifier (MP-SCPA). Cartesian combining architectures suffer reduced output power and efficiency owing to combination of out-of-phase signals. The multiphase architecture reduces the phase difference between the basis vectors that are combined, increasing the output power and efficiency compared to the Cartesian combiners. 16 equally spaced phases are produced by a phase generator with each phase's relative amplitude weighted on the bottom plate of a capacitor array and combined on a common top plate, resulting in linear amplification. The MP-SCPA delivers a peak output power and PAE of 26 dBm and 24.9%, respectively. When amplifying an LTE signal the average output power and PAE are 20.9 dBm and 15.2%, respectively while achieving <¿¿¿30 dBc ACLR and 3.5 %-rms EVM. 
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    Full Text Available 
  6. ; (, New Circuits and Systems Conference (NEWCAS), 2015 IEEE 13th International)
    An envelope elimination and restoration (EER) transmitter that comprises a class-E power amplifier and a digitally controlled current DAC modulator is presented. A switched capacitor DAC is designed to control an open-loop transconductor that operates as a current modulator, modulating the amplitude of the current supplied to a class-E PA. Such a topology allows for increased filtering of the quantization noise that is problematic in most digital PAs (DPA). The system measurements yield a peak output power and power added efficiency (PAE) of 22.5 dBm and 23.6%, respectively. When applying a WCDMA signal, the measured EVM is 1.32% and the adjacent channel power ratio (ACPR) is -37.9 dBc, while outputting 19.9 dBm at 14.3% PAE. For an LTE signal, the measured EVM is 3.72% and the ACLR is -30.2 dBc, while outputting 18.1 dBm at 10.6% PAE. 
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    Full Text Available 
  7. ; ; ; ; (, IEEE Journal of Solid-State Circuits)
    Full Text Available